1. Field of the Invention
The present invention relates to a liquid crystal display. More particularly, the present invention relates to a driving apparatus for a liquid crystal display in which an 8-bit data driver integrated circuit is used to drive 6-bit data.
2. Discussion of the Related Art
A liquid crystal display (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to display a picture. A LCD of an active matrix type provided with a switching device for each liquid crystal cell is suitable for displaying a moving picture. The switching device used for the active matrix type LCD mainly employs a thin film transistor (TFT).
FIG. 1 shows a related art LCD driving apparatus.
In FIG. 1, the related art LCD driving apparatus includes a liquid crystal display panel 2 having m×n liquid crystal cells Clc arranged in a matrix, m data lines D1 to Dm and n gate lines G1 to Gn crossing each other and thin film transistors TFT provided at the crossing of the data and gate lines, a data driver 4 for applying data signals to the data lines D1 to Dm of the liquid crystal display panel 2, a gate driver 6 for applying scanning signals to the gate lines G1 to Gn, a gamma voltage supplier 8 for supplying the data driver 4 with gamma voltages, and a timing controller 10 for controlling the data driver 4 and the gate driver 6.
The liquid crystal display panel 2 includes a plurality of liquid crystal cells Clc arranged, in a matrix, at the crossings of the data lines D1 to Dm and the gate lines G1 to Gn. The thin film transistor TFT provided at each liquid crystal cell Clc applies a data signal from each data line D1 to Dm to the liquid crystal cell Clc in response to a scanning signal from the gate line G. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is provided between a pixel electrode of the liquid crystal cell Clc and a pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line to maintain a voltage of the liquid crystal cell Clc.
The gamma voltage supplier 8 applies a plurality of gamma voltages to the data driver 4 so that analog data signals can be generated.
The timing controller 10 generates a gate control signal GCS and a data control signal DCS using synchronizing signals (or a complex synchronizing signal) supplied from a system (not shown). Herein, the gate control signal GCS is comprised of a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE, etc. The data control signal DCS is comprised of a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity signal POL, etc. The timing controller 10 re-aligns the data R, G and B input thereto to apply them to the data driver 4.
The gate driver 6 sequentially applies a scanning signal (or a gate high voltage) to the gate lines G1 to Gn in response to the gate control signal GCS from the timing controller 10. Thus, the thin film transistors TFT connected to the gate lines G1 to Gn are sequentially driven.
The data driver 4 applies pixel signals for each line to the data lines D1 to Dm every horizontal period in response to the data control signal DCS from the timing controller 10. Particularly, the data driver 4 converts digital data R, G and B input from the timing controller 8 into analog pixel signals using gamma voltages from the gamma voltage supplier 8 to apply them to the data lines D1 to Dm.
More specifically, the data driver 4 shifts a source start pulse SSP in response to a source shift clock SSC to generate sampling signals. Then, the data driver 4 sequentially receives the data R, G and B for each certain unit in response to the sampling signals to latch them. Further, the data driver 4 converts the latched data R, G and B for one line into analog data signals to apply the data signals to the data lines D1 to Dm in an enable interval of the source output enable signal SOE. Herein, the data driver 4 converts the data signals into positive signals or negative signals in response to a polarity control signal POL.
In the LCD, the timing controller 10 applies data having various bits to the data driver 4. For example, the timing controller 10 may apply 6-bit data to the data driver 4 as shown in FIG. 2A. Then, the data driver 4 converts the 6-bit data to video signals having 64 gray levels to apply the video signals to the data lines D. Presently, most notebook personal computers display a picture using 6-bit data as shown in FIG. 2A. Herein, the notebook personal computer is driven in a normally white-mode.
On the other hand, the timing controller 10 may apply 8-bit data to the data driver 4 as shown in FIG. 2B. Then, the data driver 4 converts the 8-bit data to video signals having 256 gray levels to apply the video signals to the data lines D. In the related art, computer monitors and televisions display a desired picture using 8-bit data as shown in FIG. 2B, are driven in a normally black mode.
The data driver 4 includes a 6-bit or 8-bit data driver integrated circuit that corresponds with the bit number of data supplied from the timing controller. Specifically, the related art LCD has a problem in that exclusive data driver integrated circuits are mounted to correspond to the bit number of data supplied from the timing controller 10 which leads to compatibility problems with the integrated circuit. Further, when a notebook personal computer is driven in a normally black mode, it is necessary to develop a new 6-bit only integrated circuit.